1. Field
Exemplary embodiments of the present invention relate to a semiconductor design technology, and more particularly, to testing technologies for a clock synchronization system that operates in response to an external clock.
2. Description of the Related Art
With the development of the design technology of an integrated circuit (IC) and infrastructure, the time needed to process and design the integrated circuit is gradually reduced. However, the time needed to test the integrated circuit is increased because the complexity of functions embodied by the integrated circuit is gradually increased. The time needed to design the integrated circuit is necessary only at the early stage of development, whereas the time needed to test the integrated circuit continues to be necessary in a production process. An increase of the testing time is directly related to an increase in the costs of production.
Meanwhile, the development speed of test equipment does not keep up with that of an IC chip. For example, an IC chip operates at 200 MHz, whereas the test equipment supports an operation up to 40 MHz. Furthermore, although there is test equipment having the same operation speed as an IC chip, there is a heavy burden of cost to replace the test equipment periodically corresponding to the speed of an IC chip because the test equipment is very expensive. In most cases, an IC chip operates at a lower speed in a test operation than in a normal operation due to the limitation present in the test equipment.
FIG. 1 is a construction diagram illustrating an IC chip including a conventional phase-locked loop.
Referring to FIG. 1, the IC chip 100 includes a phase-locked loop 110, a control circuit 120, an internal circuit 130 and a data transmission/reception circuit 140.
The phase-locked loop 110 generates an output clock CLK_OUT in response to an input clock CLK_IN received from the outside of the IC chip 100. The output clock CLK_OUT generated from the phase-locked loop 110 becomes an internal clock used by the IC chip 100. The input clock CLK_IN and the output clock CLK_OUT may have the same frequency or different frequencies.
The control circuit 120 performs control operations on the elements of the IC chip 100 in response to control signals CONTROL_SIGNALS received outside the IC chip 100. If the IC chip 100 is memory device, the control signals CONTROL_SIGNALS may correspond to a command and an address, and the control circuit 120 may become circuits for performing control operations corresponding to a command and an address, such as a command decoder and an address decoder. The control circuit 120 is synchronized with the output clock CLK_OUT of the phase-locked loop 110.
The internal circuit 130 performs functions unique to the IC chip 100. If the IC chip 100 is memory device, the internal circuit 130 may become a memory bank for storing or reading data in response to an instruction from the control circuit 120. Furthermore, if the IC chip 100 is a central processing unit (CPU), the internal circuit 130 may become an operation circuit for performing a variety of arithmetic operations in response to an instruction from the control circuit 120. The internal circuit 130 may also be synchronized with the output clock CLK_OUT generated from the phase-locked loop 110.
The data transmission/reception circuit 140 receives data from the outside of the IC chip 100 in synchronism with the output clock CLK_OUT generated from the phase-locked loop 110, transfers the received data to the internal circuit 130, and outputs data from the internal circuit 130 to the outside of the IC chip 100.
FIG. 2 is a block diagram illustrating the phase-locked loop 110 shown in FIG. 1.
Referring to FIG. 2, the phase-locked loop 110 includes a phase detection unit 210, a clock generation unit 220, and a division unit 230.
The phase detection unit 210 compares the phase of a feedback clock CLK_FB with the phase of the input clock CLK_IN and generates an up/down signal UP/DN, indicating that which one of the phases of the two clocks CLK_FB and CLK_IN runs ahead, based on a result of the comparison.
The clock generation unit 220 raises or lowers the frequency of the output clock CLK_OUT in response to the up/down signal UP/DN. The clock generation unit 220 includes a charge pump 221 configured to generate a charging/discharging current in response to the up/down signal UP/DN, a loop filter (or a low pass filter) 222 charged/discharged by the charging/discharging current to generate a control voltage VCTRL, and a voltage-controlled oscillator (VCO) 223 configured to generate the output clock CLK_OUT corresponding to the control voltage VCTRL.
The division unit 230 generates the feedback clock CLK_FB by dividing the output clock CLK_OUT. The division ratio N of the division unit 230 is defined by an equation 1 below.f(CLK_FB)×N=f(CLK_OUT)  Equation 1.
Where f(CLK_FB) is the frequency of the feedback clock CLK_FB, and f(CLK_OUT) is the frequency of the output clock CLK_OUT. That is, the frequency of the output clock CLK_OUT of the phase-locked loop 110 is N times of the frequency of the input clock CLK_IN.
The input clock CLK_IN of a low frequency is applied to the IC chip 100 when a test operation is performed due to the limit of test equipment as described above. For example, if the input clock CLK_IN of 500 MHz is applied to the IC chip 100 when a normal operation is performed, the input clock CLK_IN of 20 MHz may be applied to the IC chip 100 when a test operation is performed. In this state, if the division ratio of the division unit 230 is ‘1’, the clock generation unit 220 has to generate the output clock CLK_OUT of 500 MHz when a normal operation is performed and has to generate the output clock CLK_OUT of 20 MHz when a test operation is performed. In order to support the normal operation and the test operation, the clock generation unit 220 has to have an operating range (or a locking range) of about 20˜500 MHz.
As described above, it is very difficult to design the clock generation unit 220 so that the clock generation unit 220 supports an operating range having a difference of tens to several hundreds owing to a difference between the operating speeds of a normal operation and a test operation. Furthermore, there is a concern in that an area of the clock generation unit 220 is greatly increased although the clock generation unit 220 may be designed.